1. Field of the Invention
This invention relates to a method of manufacture of Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) devices and more particularly to raised source/drain MOSFET devices.
2. Description of Related Art
In the past, CMOS devices have been constructed by using a combination of photoresist masks and gate polysilicon to mask implanted shallow extensions of the source/drain regions. Implantation follows formation of a gate dielectric and the polysilicon gate. After implantation the substrate is annealed to activate the implanted dopant.
As devices become smaller and more advanced, several problems arise related to this process sequence. There is a tradeoff between the resistance of the extension and problems stemming from the short channel effect. If the extension is heavily implanted, then it has low resistance, but it is impossible to avoid a relatively deep junction and the associated short channel effect from implanted dopant that scatters laterally. Furthermore, multiple high temperature annealing steps are required for activation during construction of CMOS devices. These high temperature annealing steps, in combination with transient enhanced diffusion stemming from implant damage, further contribute to unwanted spreading of dopant into regions where its presence is destructive. Raised source/drain processes avoid some of the problems mentioned. In particular, a set of thicker low resistance source and drain regions are obtained. Since the implanted raised source/drain regions lie above the channel, a portion of the scattering from implanted ions takes place above the channel region. However, some scattering occurs and activation annealing steps and transient enhanced diffusion can contribute to the spreading of dopant. Conventional selective epitaxy, which uses a relatively high deposition temperature and which is usually considered for raised source/drain (S/D) regions, is a higher temperature process that contributes to dopant diffusion and limits gate and dielectric choices for advanced devices and does not enable in-situ doping.
It is also difficult to provide a process sequence and low temperature epitaxial precleaning which does not contribute to low temperature dopant spread.
U.S. Pat. No. 6,235,645 of Habuka et al. for “Process for Cleaning for Silicon Semiconductor Substrates” describes removing organic materials and metal impurities on the surface of the substrate: The process prevents regrowth of a natural oxide film by employing highly reductive atmospheres with a trace of water inherently included in the film as a reaction initiating catalyst. An organic material is decomposed in a HF/H2 mixed gas atmosphere which is preferably set in the range of from 0° C. to 600° C. Cleaning for epitaxial growth is described and cleaning temperatures involving temperatures as high as 1000° C. or more are indicated.
U.S. Pat. No. 5,227,330 of Agnello et al. for “Comprehensive Process for Low Temperature Si Epitaxial Growth” and U.S. Pat. No. 5,378,651 of Agnello et al. for “Comprehensive Process for Low Temperature Epitaxial Growth” describe methods of fabrication of silicon devices and, more particularly, methods of growing of epitaxial layers of silicon by deposition at low temperatures. The Agnello et al. patents describe precleaning when producing low temperature epitaxy (LTE) at atmospheric pressure, and methods for controlling the relative amount of silicon growth on silicon dioxide vs. single crystal. Those patents are directed to producing greater growth on silicon oxide than on single crystal silicon, so that a thicker (and therefore more conductive) extrinsic base can be grown for bipolar transistors instead of CMOS. While precleaning for LTE at low pressure at atmospheric pressure is described, the precleaning step does not produce specialized shapes.
U.S. Pat. No. 6,110,787 of Chen et al. for “Method of Fabricating a MOS Device” describes forming a raised source/drain device with raised STI raised or isolation regions with isolation spacers on the sidewalls, and a gate conductor having gate spacers. Any oxide or contamination on the substrate is removed by using a wet etch of dilute HF. An intrinsic epitaxial silicon, amorphous silicon, or polysilicon layer is selectively deposited, preferably by Selective Epitaxial Growth (SEG). While Chen et al. uses selective epitaxy, it does not suggest use of LTE. Moreover, Chen et al. does not describe an embodiment which is doped in situ instead of being ion implanted.
U.S. Pat. No. 6,248,637 of Yu for “Process for Manufacturing MOS Transistors Having Elevated Source and Drain Regions” describes disposable spacers formed by oxidizing a polysilicon gate electrode over a silicon nitride gate dielectric. Sidewalls of the gate electrode are oxidized selectively providing a semi-conductor and silicide material above the source/drain locations, doping the source location and the drain location to form elevated source and drain regions, driving in the dopant with a high temperature Rapid Thermal Anneal (RTA) followed by a removing the oxide structure to create an opening to use for a halo or pocket ion implant plus forming source/drain extensions through the openings which are self-aligned with the gate electrode stack, followed by a low temperature RTA.
U.S. Pat. No. 6,137,149 of Kodama for “Semiconductor Device Having Raised Source-Drains and Method of Fabricating the Same” describes a method of forming an FET including raised source and drain layers and a particular shaped insulating film formed on a sidewall of a gate electrode. HF is used to remove natural oxide films formed on regions of silicon substrate where source and drain regions to be formed later. The raised source/drain layers are formed by selective epitaxial growth. The second embodiment relies on a chemical difference (using HF, sulfuric and acetic acid etchant) between an amorphous silicon film over silicon oxide and single crystal silicon to remove the silicon only from the silicon oxide surface.